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Leo Panda

Principal Design Verification Engineer
PROFESSIONAL SUMMARY

Principal Design Verification Engineer with 13+ years of experience leading block and SoC verification for high-performance CPU, interconnect, and AI accelerator designs. Deep expertise in SystemVerilog, UVM, assertions, coverage closure, and verification planning. Known for improving first-silicon success, accelerating regressions, and mentoring teams across complex, schedule-driven programs.

SKILLS
SystemVerilog
UVM
SVA / Assertions
Coverage Closure
Formal Verification
Python Automation
Emulation / FPGA Debug
SoC Verification
Jasper / VC Formal / VCS
PROFESSIONAL EXPERIENCE
Marvell Technology
SemiconductorData Infrastructure
San Jose, CA
Principal Design Verification Engineer
UVMSoC Verification
May 2019 - Present
  • Led verification strategy for high-performance interconnect and cache-coherent IP, delivering coverage closure above 98% and supporting first-pass silicon success on two SoC programs.
  • Architected reusable UVM environments, assertions, and scoreboards that cut testbench development time by 30% across multiple derivative designs.
  • Drove cross-functional debug with design, architecture, and firmware teams, reducing critical bug turnaround from five days to two days during tapeout phase.
  • Improved regression throughput by 40% through Python-based automation, optimized test selection, and failure triage workflows across a 12,000-test nightly suite.
  • Mentored six verification engineers on planning, constrained-random methodology, and coverage analysis, increasing team productivity and review quality across globally distributed teams.
NVIDIA
SemiconductorAI Hardware
Santa Clara, CA
Senior Design Verification Engineer
SystemVerilogAssertions
Jul 2013 - Apr 2019
  • Verified memory subsystem and DMA blocks for accelerator-class SoCs using SystemVerilog and UVM, closing all planned functional coverage and protocol compliance milestones.
  • Developed assertion-based checkers and reference models that uncovered 45 high-priority bugs before netlist freeze, improving design quality at block sign-off.
  • Collaborated with emulation and post-silicon teams to reproduce corner-case failures, shortening debug cycles and strengthening pre-silicon to silicon correlation.
  • Owned verification plans, test reviews, and milestone reporting for two IPs, consistently meeting schedule commitments across aggressive quarterly release targets.
SELECTED PROJECTS
Coherent Interconnect SoC Integration Verification - Verification Lead
Jul 2023 - Mar 2024
  • Defined top-level verification strategy for a coherent interconnect subsystem, aligning block environments, scoreboards, and end-to-end checking across six dependent IP teams.
  • Drove performance-focused scenario development and coverage reviews, helping achieve sign-off with zero critical escape defects before tapeout readiness review.
  • Partnered with architects and firmware teams to validate coherency, ordering, and error handling behaviors under high-traffic multi-core stress conditions.
Reusable UVM Verification Framework for DMA IP - Principal DV Engineer
Feb 2021 - Nov 2021
  • Led reusable UVM environment enhancement for a next-generation DMA engine, introducing configurable agents, protocol checkers, and reference models shared across three programs.
  • Reduced environment bring-up time for new derivatives by standardizing sequences, coverage models, and regression hooks used by distributed verification teams.
  • Strengthened bug triage efficiency through structured debug dashboards and failure categorization, enabling faster root-cause isolation during nightly regressions.
EDUCATION
Purdue University
SemiconductorVLSI
West Lafayette, IN
Master of Science in Electrical and Computer Engineering
Aug 2009 - May 2011

Focus on digital IC design, computer architecture, and verification methodologies.

University of California, Irvine
STEMDigital Design
Irvine, CA
Bachelor of Science in Electrical Engineering
Sep 2005 - Jun 2009

Foundation in logic design, embedded systems, and semiconductor device fundamentals.

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